Formal Definition
Module instantiation provides a means of nesting modules descriptions.
Systemverilog Spec
Simplified Syntax
module_name [parameter_value_assignment] module_instance ;
Description
If you are running icarus verilog, then you should give the following command iverilog stimulus.v main.v where file stimulus.v is the testbench containing the `timescale directive and the main.v is the main program. Verilog Blocking and Non-blocking. Verilog supports blocking and non-blocking assignments statements within the always block with their different behaviors. The blocking assignment is similar to software assignment statements found in most popular programming languages. Module Instantiation. Formal Definition. Module instantiation provides a means of nesting modules descriptions. Simplified Syntax. Modulename parametervalueassignment moduleinstance; Description. Modules can be instantiated from within other modules. When a module is instantiated, connections to the ports of the module must be specified. Verilog vs VHDL: Explain by Examples 32. Verilog code for Clock divider on FPGA 33. How to generate a clock enable signal in Verilog 34. Verilog code for PWM Generator 35. Verilog coding vs Software Programming. Defines the size of the memory block. Note the use of the Verilog as there is in VHDL. Just like the shift register model from November, the parameterisable bidirectional port.
Modules can be instantiated from within other modules. When a module is instantiated, connections to the ports of the module must be specified. There are two ways to make port connections. One is connection by name, in which variables connected to each of module inputs or outputs are specified in a set of parenthesis following the name of the ports. In this method order of connections is not significant. See Example 1.
The second method is called ordered connection. In this method the order of the ports must match the order appearing in the instantiated module. See Example 2. When ports are connected by name it is illegal to leave any ports unconnected. This may occur when ports are connected by order. See Example 3.
What happens if you leave a port unconnected depends on the type of the port. If you are connecting net type ports, unconnected bits are driven with high impedance. In other cases, bits are driven with unknown values.
Module instantiations can create an array of instances. To create theses instances, range specifications have to be declared after the module name. The array of instances can save you time in writing code and provide a way to enrich your readability, see Example 4
Examples
Example 1
module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
dff inst_1 (.d(data), .q(net_1), .clk(clock));
dff inst_2 (.clk(clock), .d(net_1), .q(q_out));
endmodule
In the top module there are two instantiations of the 'dff' module. In both cases port connections are done by name, so the port order is insignificant. The first port is input port 'd', the second is output 'q' and the last is the clock in the 'inst_1'. In the dff module the order of ports is different than either of the two instantiations.
Example 2
module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
dff inst_1 (clock, data, net_1);
dff inst_2 (clock, net_1, q_out);
endmodule
Example 3
dff inst_1 (clock, , net_1);
Second port is unconnected and has the value Z because it is of the net type.
Example 4
module my_module (a, b, c);
input a, b;
output c;
assign c = a & b ;
endmodule
module top (a, b, c) ;
input [3:0] a, b;
output [3:0] c;
my_module inst [3:0] (a, b, c);
endmodule
For Loop In Systemverilog
Important Notes
If ports are connected by name it is illegal to leave any ports unconnected.
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